Data Check - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The set_data_check command sets the equivalent of a setup or hold timing check between two pins in a design. For example, this constraint can be used to report timing on asynchronous interfaces. This command is ignored by the implementation tools and must only be used for timing reporting purposes, typically by expert users.