Using the UltraFast Design Methodology DRCs - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
Release Date
2020.2 English

The Vivado Design Suite contains a set of methodology-related DRCs you can run using the report_methodology Tcl command. This command has rules for each of the following design stages:

  • Before synthesis in the elaborated RTL design to validate RTL constructs
  • After synthesis to validate the netlist and constraints
  • After implementation to validate constraints and timing related concerns.
Recommended: For maximum effect, run the methodology DRCs at each design stage and address any issues prior to moving to the next stage.

For more information on the design methodology DRCs, see the report_methodology Tcl command in the Vivado Design Suite Tcl Command Reference Guide (UG835).