Coding Shift Registers and Delay Lines - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

In general, a shift register is characterized by some or all of the following control and data signals:

  • Clock
  • Serial input
  • Asynchronous set/reset
  • Synchronous set/reset
  • Synchronous/asynchronous parallel load
  • Clock enable
  • Serial or parallel output

Xilinx devices contain dedicated SRL16 and SRL32 resources (integrated in LUTs). These allow efficiently implemented shift registers without using flip-flop resources. However, these elements support only LEFT shift operations, and have a limited number of I/O signals:

  • Clock
  • Clock Enable
  • Serial Data In
  • Serial Data Out

In addition, SRLs have address inputs (A3, A2, A1, A0 inputs for SRL16) determining the length of the shift register. The shift register may be of a fixed static length, or it may be dynamically adjusted.

In dynamic mode each time a new address is applied to the address pins, the new bit position value is available on the Q output after the time delay to access the LUT. Synchronous and asynchronous set/reset control signals are not available in the SRL primitives. However, if your RTL code includes a reset, the Xilinx synthesis tool infers additional logic around the SRL to provide the reset functionality.

To obtain the best performance when using SRLs, Xilinx recommends that you implement the last stage of the shift register in the dedicated Slice register. The Slice registers have a better clock-to-out time than SRLs. This allows some additional slack for the paths sourced by the shift register logic. Synthesis tools will automatically infer this register unless this resource is instantiated or the synthesis tool is prevented from inferring such a register because of attributes or cross hierarchy boundary optimization restrictions.

Xilinx recommends that you use the HDL coding styles represented in the Vivado Design Suite HDL Templates.

When using registers to obtain placement flexibility in the chip, turn off SRL inference using the attribute:


For more information about synthesis attributes and how to specify those attributes in the HDL code, see the Vivado Design Suite User Guide: Synthesis (UG901).