Assessing the Maximum Frequency of the Design - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

You can define and assess the maximum frequency (FMAX) in the following ways:

  • The FMAX (MHz) a design can run on hardware in a given implementation = 1000/(T-WNS), with WNS positive or negative.
  • The FMAX (MHz) a design can run on a given architecture = 1000/(T-WNS), only if WNS < 0. You must decrease T and rerun synthesis or implementation until WNS < 0. Different synthesis and implementation strategies are needed to get the best achievable FMAX.


  • T is the target clock period (ns).
  • WNS is the worst negative slack (ns) of the target clock.
Note: The FMAX value is not explicitly provided in the report_timing or report_timing_summary report.