Design Creation with RTL - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
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2020.2 English

After planning your device I/O, planning how to lay out your PCB, and deciding on your use model for the Vivado® Design Suite, you can begin creating your design. Design creation includes:

  • Planning the hierarchy of your design
  • Identifying the IP cores to use and customize in your design
  • Creating the custom RTL for interconnect logic and functionality for which a suitable IP is not available
  • Creating timing, power, and physical constraints
  • Specifying additional constraints, attributes, and other elements used during synthesis and implementation

When creating your design, the main points to consider include:

  • Achieving the desired functionality
  • Operating at the desired frequency
  • Operating with the desired degree of reliability
  • Fitting within the silicon resource and power budget

Decisions made at this stage affect the end product. A wrong decision at this point can result in problems at a later stage, causing issues throughout the entire design cycle. Spending time early in the process to carefully plan your design helps to ensure that you meet your design goals and minimize debug time in lab.