Applying Common Timing Closure Techniques - 2020.2 English - UG949

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs
Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The following techniques can help with design closure on challenging designs. Before attempting these techniques, ensure that the design is properly constrained and that you identify the main issue that affects the top violating paths.

Recommended: Xilinx recommends running the report_qor_suggestions Tcl command to identify and apply many of these techniques automatically. For more information, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).