Interconnect Congestion Level in the Device Window - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs
Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The Interconnect Congestion Level metric highlights the largest contiguous area in which routing resources are overused. By default, this metric is based on estimation, which is similar to the congestion level after initial routing. Actual routing can also be displayed if routing exists. After placement or after routing, you can display this congestion metric by right-clicking in the Device window and selecting Metric > Interconnect Congestion Level.

The Interconnect Congestion Level metric provides a quick visual overview of any congestion hotspots in the device. The following figure shows a placed design with several congested areas. This metric is based on the current interconnect demand and availability with a threshold of 0.9 (i.e., 90% routing usage). The range is 0.1 to 0.9.

You can visualize congestion based on:

  • Direction: North, South, East, West, Vertical, Horizontal
  • Type: Short, Long, Global
  • Style: Estimated, Routed, Mixed
Figure 1. Example of Interconnect Congestion Level in the Device Window

Use the Routing Congestion per CLB, which is based on estimation and not actual routing. After placement or after routing, you can display this congestion metric by right-clicking in the Device window and selecting Metric > Vertical and Horizontal Routing Congestion per CLB. This provides a quick visual overview of any congestion hotspots in the device. The following figure shows a placed design with several congested areas due to high utilization and netlist complexity.

Note: Use this method for 7 series and UltraScale devices only.
Figure 2. Example of Congestion per CLB in the Device Window