When Instantiation Is Desirable - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Instantiation might be desirable when the synthesis tool mapping does not meet the timing, power, or area constraints; or when a particular feature within a device cannot be inferred.

With instantiation, you have total control over the synthesis tool. For example, to achieve better performance, you can implement a comparator using only LUTs, instead of the combination of LUT and carry chain elements usually chosen by the synthesis tool.

Sometimes instantiation may be the only way to make use of the complex resources available in the device. This can be due to:

  • HDL Language Restrictions

    For example, it is not possible to describe double data rate (DDR) outputs in VHDL because it requires two separate processes to drive the same signal.

  • Hardware Complexity

    It is easier to instantiate the I/O SerDes elements than to create synthesizable description.

  • Synthesis Tools Inference Limitations

    For example, synthesis tools currently do not have the capability to infer the hard FIFOs from RTL descriptions. Therefore, you must instantiate them.

    If you decide to instantiate a Xilinx primitive, see the appropriate User Guide and Libraries Guide for the target architecture to fully understand the component functionality, configuration, and connectivity.

    In case of both inference as well as instantiation, Xilinx recommends that you use the instantiation and language templates from the Vivado Design Suite language templates.

Following are tips:

  • Infer functionality whenever possible.
  • When synthesized RTL code does not meet requirements, review the requirements before replacing the code with device library component instantiations.
  • Consider the Vivado Design Suite language templates when writing common Verilog and VHDL behavioral constructs or if necessary instantiating the desired primitives.