Reset Coding Example: Multiplier with Synchronous Reset - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

To take advantage of the existing DSP primitive features, the following example shows a multiplier with synchronous reset.

Figure 1. Multiplier with Pipeline Registers (Synchronous Reset)

In this circuit, the DSP48 primitive is inferred with all pipeline registers packed within the DSP primitive (AREG/BREG=1, MREG=1, PREG=1).

This coding example has the following advantages:

  • Optimal resource usage
  • Better performance and lower power
  • Lower number of endpoints