Synthesis Attributes - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Synthesis attributes allow you to control the logic inference in a specific way. Although synthesis algorithms are set to give the best results for the largest number of designs, there are often designs with differing requirements. In this case, you can use attributes to alter the design to improve QoR. For information on the attributes supported by synthesis, see the Vivado Design Suite User Guide: Synthesis (UG901).

Power Tip: Evaluate synthesis settings carefully, because these settings can have a considerable impact on the power consumption of a design. For example, a low setting for the control set threshold increases the usage of register clock enables at the expense of less dense packing. Run the report_power command after synthesis to evaluate the impact of synthesis settings on power.
Note: Before retargeting your design to a new device, Xilinx recommends reviewing any synthesis attributes from previous design runs that target older devices.

When using the KEEP, DONT_TOUCH, and MAX_FANOUT attributes, be aware of the special considerations described in the following sections.