High Fanouts in Critical Paths - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English
High fanout nets are much easier to deal with early in the design process. What constitutes too high of a fanout is often dictated by performance requirements and the construction of the paths. You can use the following techniques to address issues with high fanout nets.
Recommended: Identify high fanout nets using the report_high_fanout_nets Tcl command after synthesis. Monitor the impact of these nets on design performance as you progress through the implementation process.