You can use a gigabit transceiver output pin (e.g., a recovered clock) as the primary clock root as shown in the following figure.
Figure 1. create_clock on a Primitive Pin
Constraint example:
create_clock -name txclk -period 6.667 [get_pins gt0/TXOUTCLK]Recommended: For designs that
target 7 series devices, Xilinx recommends also defining the GT incoming clocks, because the
Vivado tools calculate the expected clocks on the
GT output pins and compare these clocks with the user-created clocks. If the clocks
differ or if the incoming clocks to the GT are missing, the tools issue a methodology
check warning.
Note: For designs that target
UltraScale™
devices, Xilinx does not
recommend defining a primary clock on the output of GTs, because GT clocks are
automatically derived when the related board input clocks are defined.