Reviewing and Cleaning DRCs - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
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2020.2 English

The report_drc command runs design rule checks (DRCs) to look for common design issues and errors. There are multiple rule decks. The default rule deck checks the following:

  • Post-synthesis netlist
  • I/O, BUFG, and other placement specific requirements
  • Attributes and wiring on MGTs, IODELAYs, MMCMs, PLLs and other primitives
Recommended: Review and correct DRC violations as early as possible in the design process to avoid timing or logic related issues later in the implementation flow.
Tip: For DRC violations that can be safely ignored, you can use the waiver mechanism to waive the violations. For details, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).