Power Closure - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

Given the importance of power, the Vivado tools support methods for obtaining an accurate estimate for power, as well as providing some power optimization capabilities. For additional information, see the Vivado Design Suite User Guide: Power Analysis and Optimization (UG907).

Recommended: When targeting UltraScale and UltraScale+™ devices and using the Explore directives or Explore-based strategies, you must manually enable block RAM power optimization by running power_opt_design or using opt_design -bram_power_opt after opt_design runs. Xilinx recommends targeting block RAMs to achieve power reduction.