Adding False Path Constraints - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

False path exceptions can be added to timing paths to ignore slack computation on these paths. It is usually difficult to prove that a path does not need timing to be functional, even with simulation tools. Xilinx does not usually recommend using a false path unless the risk associated with it has been properly assessed and appear to be acceptable.