Input Ports - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

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2020.2 English

You can use an input port as the primary clock root as shown in the following figure.

Figure 1. create_clock for Input Ports

Constraint example:

create_clock -name SysClk -period 10 -waveform {0 5} [get_ports sysclk]

In this example, the waveform is defined to have a 50% duty cycle. The -waveform argument is shown above to illustrate its usage and is only necessary to define a clock with a duty cycle other than 50%. For a differential clock input buffer, the primary clock only needs to be defined on the P-side of the pair.