All designs come with a minimum set of physical constraints, especially for I/O
location, and sometimes for clocking and logic placement. While I/O location cannot be
modified when the design is ready for timing closure, physical constraints such as
Pblocks and LOC must be analyzed. Use the report_design_analysis Timing Path Characteristics table to identify the
presence of several Pblocks constraints on each critical path.
In the Vivado IDE Properties window, you can select the path in the Timing Path Characteristic table to review which Pblocks are constraining cells in the path. Consider removing one or several Pblock constraints if the constraints force logic spreading.