Checking for Multi-Fanout on the Output of Read Data Registers - 2020.2 English

UltraFast Design Methodology Guide for Xilinx FPGAs and SoCs

Document ID
UG949
Release Date
2021-02-18
Version
2020.2 English

The fanout of the data output bits from the memory array must be 1 for the second register to be absorbed by the RAM primitive. This is illustrated in the following figure.

Figure 1. Multiple Fanout Preventing Block RAM Output Register Inference