HDMI 1.4 and 2.0 protocols use three GT channels in a Quad leaving one unused. The fourth GT channel can be enabled and used as the TX TMDS Clock source instead of being generated by DCM (MMCM or PLL)
When this option is enabled, the TX TMDS Clock
ports, tx_tmds_clk_p/n output ports are disabled and are
replaced by phy_txn/p_out[3].
A pattern generator module is added in the Video PHY Controller architecture to generate the specific pattern needed to generate the required TMDS clock frequency from the fourth GT channel. The pattern generator control register is located at offset 0x340 and is programmed based on the line rate to TMDS clock ratio. The pattern generator supports ratios of 10, 20, 30, 40, and 50. For example, in a typical HDMI 1.4 resolution such as 1080p60, the line rate per channel is 1.485 Gbps and the TMDS clock is 148.5 MHz, thus giving a ratio of 10. For low line rate resolutions such as 480P60 which needs an oversampling technique (for example, x3) to be transmitted, the ratio is computed as the actual line rate per channel (270 Mbps x 3) over TMDS clock (27 MHz), which gives a ratio of 30. For HDMI 2.0 resolution such as 4KP60, the line rate is 5.94 Gbps and the TMDS clock is 148.5 MHz, thus giving a ratio of 40.
Take note that a corresponding pin assignment constraint
must be added in the top-level XDC for designs targeting 7 series devices such as Artix 7 and
Kintex 7, to properly connect the phy_txn/p_out[3] ports to their corresponding MGT pins. The
additional constraint is not needed when targeting UltraScale and UltraScale+ devices
because the pin assignments are already handled within the GT Wizard in the Video PHY Controller. If the pin assignment constraints in the
top-level XDC are different, the pin assignment generated within the GT wizard
overwrites the ones in the top-level XDC and might cause critical warning messages.