GT Channels Interface Ports - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. GT Channels Ports
Name I/O Clock Domain Description
gttxpippmen_in 1 I TXUSRCLK2 Width: 1* Num. channels. Available when TXPI_Port_EN user parameter is enabled. Connects to TXPIPPMEN on transceiver channel primitives.
gttxpippmovrden_in 1 I TXUSRCLK2 Width: 1* Num. channels. Available when TXPI_Port_EN user parameter is enabled. Connects to TXPIPPMOVRDEN on transceiver channel primitives.
gttxpippmpd_in 1 I TXUSRCLK2 Width: 1* Num. channels. Available when TXPI_Port_EN user parameter is enabled. Connects to TXPIPPMPD on transceiver channel primitives.
gttxpippmsel_in 1 I TXUSRCLK2 Width: 1* Num. channels. Available when TXPI_Port_EN user parameter is enabled. Connects to TXPIPPMSEL on transceiver channel primitives.
gttxpippmstepsize_in 1 I TXUSRCLK2 Width: 5* Num. channels. Available when TXPI_Port_EN user parameter is enabled. Connects to TXPIPPMSTEPSIZE on transceiver channel primitives.
phy_rxp_in[n-1:0] 2 I RX Serial Clock Positive differential serial input to the transceiver
phy_rxn_in[n-1:0] 2 I RX Serial Clock Negative differential serial input to the transceiver
phy_txp_out[n-1:0] 3 O TX Serial Clock Positive differential serial output from the transceiver
phy_txn_out[n-1:0] 3 O TX Serial Clock Negative differential serial output from the transceiver
vid_phy_tx_axi4s_ch<i>_tready 4 O TXUSRCLK2

AXI4-Stream based tready indicator
vid_phy_tx_axi4s_ch<i>_tvalid 4 I TXUSRCLK2

AXI4-Stream based tvalid indicator
vid_phy_tx_axi4s_ch<i>_tdata 4 I TXUSRCLK2 AXI4-Stream based tdata bus

GT Mapping: TXDATA_IN

Width: TX_DATA_WIDTH
vid_phy_tx_axi4s_ch<i>_tuser 4 I TXUSRCLK2 AXI4-Stream based tuser bus

GT Mapping: {TXCHARDISPVAL, TXCHARDISPMODE, TXCHARISK}

In UltraScale and UltraScale+ devices, TXCHARDISPVAL and TXCHARDISPMODE are represented using TXCTLR0 and TXCTRL1.

Width: TX_USER_WIDTH (For DisplayPort 12 bits)
vid_phy_rx_axi4s_ch<i>_tready 4 I RXUSRCLK2 AXI4-Stream based tready indicator
vid_phy_rx_axi4s_ch<i>_tvalid 4 O RXUSRCLK2 AXI4-Stream based tvalid indicator.
vid_phy_rx_axi4s_ch<i>_tdata 4 O RXUSRCLK2 AXI4-Stream based tdata bus

GT Mapping: RXDATAOUT

Width: RX_DATA_WIDTH
vid_phy_rx_axi4s_ch<i>_tuser 4 O RXUSRCLK2 AXI4-Stream based tuser bus

GT Mapping: {RXNOTINTABLE, RXDISPERR, RXCHARISK}

In UltraScale and UltraScale+ devices, RXNOTINTABLE, RXDISPERR, RXCHARISK are represented using RXCTRL0, RXCTR1 and RXCTRL3.

  • bit 0 - RXCHARISK or RXCTRL2 (UltraScale and UltraScale+)
  • bit 1 - RXDISPERR or RXCTRL1 (UltraScale and UltraScale+)
  • bit 2 - RXNOTINTABLE or RXCTRL0(UltraScale and UltraScale+)

Width: RX_USER_WIDTH (For DisplayPort: 12 bits)
  1. Used for UltraScale and UltraScale+ devices.
  2. n is the number of RX channels.
  3. n is the number of TX channels.
  4. <i> is the transceiver channel index.