Revision History - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
Release Date
2.2 English

The following table shows the revision history for this document.

Section Revision Summary
11/03/2023 v2.2
NA Added support for PLL Clock Primitive for HDMI Protocol for GTHE4 and GTYE4
Parameter Description Added an IP symbol in parameters.
User Parameters Added a column for TX/RX Clock Primitive.
10/19/2022 v2.2
HDMI Clocking Added HDMI clocking table with example settings
Using the Fourth GT Channel as the TX TMDS Clock Source and DisplayPort Protocol with GTHE3 and GTHE4 Transceiver Updated screens
AUX Channel Removed from I/O Standard and Placement - DisplayPort
12/10/2021 v2.2
General updates Editorial updates only, No technical content updates.
06/30/2021 v2.2

IP Facts

Product Specification

Updated notes.

Updated the table RX Initialization (RXI) Register (0x0024)

Updated the table Clock Detector (HDMI) Control Register (0x0200)

08/07/2020 v2.2

GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Disabled

GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Enabled

Clarifications added.
Using the Fourth GT Channel as the TX TMDS Clock Source Recommendation note added.
Required Constraints Updated constraints information for PHY.
12/06/2019 v2.2
MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL) Register (0x0140) Bit 12 added
DisplayPort Clocking

Clocking tables updated

Important note updated

GTXE2*/GTHE3 Clocking When Transmit Buffer Bypass is Enabled BUFG_GT added to figure

DisplayPort Protocol with GTXE2 Transceivers

DisplayPort Protocol with GTHE3 and GTHE4 Transceiver

Clarification note added
05/22/2019 v2.2
TX TMDS Pattern Generator Control Register (0x0340) Updated TX TMDS bits
UltraScale GTHE3, UltraScale+ GTHE4 and GTYE4 HDMI Implementation Update Bits Per Pixel=48 (UXGA 60) in Video Formats table
HDMI Reference Clock Requirements Reference clock constraint updated
Clock Placement Reference clock constraint updated
Board Design Guidelines - HDMI GT receiver guidance updated
Known Issues Primary clock critical warnings note added
12/05/2018 v2.2
  • Added support for GTYE4 support in DisplayPort Clocking section
  • Added links to device datasheets
  • Added links to example designs
04/04/2018 v2.2
Designing with the Core
  • Added AMD UltraScale+™ GTYE4 support
  • Enabled 4KP24/25/30 10 BPC support in AMD UltraScale+™ /AMD UltraScale+™ + CPLL
  • Enabled usage of fourth GT channel as TX TMDS Clock source for HDMI
  • Converted MMCM control to DRP based accesses
11/29/2017 v2.0
DisplayPort Clocking
  • Updated to remove GTPE2 support for DisplayPort
10/04/2017 v2.1
Overview and Designing with the Core
  • Updated to remove GTHE2 support
07/14/2017 v2.0
IP Facts
  • Updated AMD Artix™ 7 support in IP Facts
04/05/2017 v2.0
Clocking and HDMI Clocking Added new section.
  • Added Clocking section
  • Added Video PHY HDMI Generated Clocks section
  • Updated Bank section
  • Updated I/O Standard and Placement section
I/O Standard and Placement - DisplayPort Updated.
06/08/2016 v2.0
  • Updated for GTHE4 support
04/06/2016 v2.0
IP Facts, Unsupported Features, and Design Flow Steps
  • Updated Features in IP Facts
  • Updated Unsupported Features in Overview chapter
  • Updated NI-DRU and Performance sections in Product Specification chapter
  • Updated User Clock Source section
  • Updated PHY Controller Ports table
  • Updated Register Map table
DisplayPort Clocking, Program and Interrupt Flow Added.
11/18/2015 Version 2.0
Initial release. N/A