HDMI Reference Clock Requirements - 2.2 English

The Video PHY Controller HDMI application requires a system clock and a maximum of three GT reference clock inputs:

• System Clock
• HDMI TX from an external clock generator
• HDMI RX in CDR mode (normal operation)
• HDMI RX NI-DRU mode

The system clock should drive the vid_phy_sb_aclk, vid_phy_axi4lite_aclk, and drpclk (for UltraScale+/UltraScale devices only).The ports should be connected to a valid clock such as a 50 MHz, 100 MHz, or 150 MHz clock. The system clock must be properly buffered (that is, BUFG) before it can be used and connected.

The HDMI TX and RX reference clock (TMDS clocks) input frequency varies according to the input video and both are maximized at 297 MHz. Starting in Vivado 2018.3, the corresponding reference clock frequencies must be constrained at the Vivado Project top level XDC file at 297 MHz, that is, create_clock -period 3.367 [get_ports <HDMI TX/RX REFCLK portname>]. The NI-DRU reference clock frequency is fixed and is dependent on the transceiver type as follows:

GTXE2

125 MHz

GTHE3, GTHE4, and GTYE4

156.25 MHz

GTPE2

100 MHz

Starting in Vivado 2018.3, the NI-DRU reference clock frequency must be constrained at the Vivado Project top level XDC file at a specified frequency; that is, for GTHE4: create_clock -period 6.400 [get_ports <NI-DRU REFCCLK portname>]

The following figure illustrates the full reference clock requirement connections.

Figure 1. Video PHY Controller HDMI Reference Clock Connections

The HDMI TX reference clock comes from an external programmable clock generator capable of generating a range of frequencies from the minimum PLL reference clock (see HDMI TX Oversampled Reference Clock Requirements) to the maximum TMDS clock for supported video formats. For example, the Video PHY Controller TX uses the GTXE2 QPLL and supports up to 4Kp60 at two pixels per clock. This means that the programmable clock generator must be able to generate frequencies from 74.125 MHz to 297 MHz. For resolutions requiring a lower TMDS clock than the minimum PLL reference clock, the Video PHY Controller uses the oversampling technique (see the following section for details).

The txrefclk port is accompanied by the tx_refclk_rdy port to indicate a lock condition. The tx_refclk_rdy port has three requirements:

• Connected to the external clock generator lock pin by default or can be toggled through GPIO. It must be toggled (deasserted then asserted) for every video format change. Alternatively, the TX Frequency Reset bit (bit 3) of the Clock Detector Control register (0x200) can be set if the tx_refclk_rdy port is active.
• It can only be asserted when the clock at txrefclk_p/n port is stable.
• At AXILITE CLK = 100 MHz, the tx_refclk_rdy minimum hold time is 5 us and 4 ms for fast switching and non-fast switching modes respectively.

TX REFCLK frequency detection is sensitive only to the behavior of the tx_refclk_rdy port, a change that triggers the clock detector to issue the TX frequency change event. The external clock generator is set up for the desired TX clock frequency, which means that the Video PHY Controller TX should get the requested frequency from the clock generator. Because the assumption is that Video PHY Controller gets the correct clock, it only requires the LOCK event to trigger the TX reconfiguration that is represented by the assertion of tx_refclk_rdy.