Clocking and Reset Interface Ports

Table 1. Clocking and Resets Ports
Name	I/O	Clock Domain	Description
mgtrefclk0_pad_(p/n)_in	I		Available when Advanced Clock mode is disabled or when GTREFCLK0 is selected as one of the input clock sources in HDMI. User clock module instantiates input buffers. 7 series: Connects to GTREFCLK0 UltraScale and AMD UltraScale+™ : Connects to GTREFCLK00, GTREFCLK01.
mgtrefclk1_pad_(p/n)_in	I		Available when Advanced Clock mode is disabled or when GTREFCLK1 is selected as one of the input clock sources in HDMI. User clock module instantiates input buffers. 7 series: Connects to GTREFCLK1. UltraScale and UltraScale+: Connects to GTREFCLK10, GTREFCLK11.
mgtrefclk0_in	I		Available when Advanced Clock mode is enabled. You must instantiate input buffers at the system level. 7 series: Connects to GTREFCLK0.
mgtrefclk1_in	I		Available when Advanced Clock mode is enabled. You must instantiate input buffers at the system level. 7 series: Connects to GTREFCLK1.
mgtrefclk(0/1)_odiv2_in	I		Available when Advanced Clock mode is enabled and GTREFCLK0/1 is selected as one of the input clocks. This must be connected to the ODIV2 output of the gtrefclk0/1_in input buffer. The ODIV2 output must be configured to output a divided-by-1 clock.
gtnorthrefclk(0/1)_in	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTNORTHCLK0/1 is selected as one of the input clock sources. You must instantiate input buffers at the system level. Connects to GTNORTHREFCLK_0/1 ports.
gtsouthrefclk(0/1)_in	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTSOUTHREFCLK0/1 is selected as one of the input clock sources. You must instantiate input buffers at the system level. Connects to GTSOUTHREFCLK_0/1 ports.
gtnorthrefclk(0/1)_odiv2_in (For UltraScale and UltraScale+ HDMI)	I		Available when GTNORTHREFCLK0/1 is selected as one of the input clock sources. This must be connected to the ODIV2 output of the gtnorthrefclk0/1_in input buffer. The ODIV2 output must be configured to output a divided-by-1 clock.
gtsouthrefclk(0/1)_odiv2_in (For UltraScale and UltraScale+ HDMI)	I		Available when GTSOUTHREFCLK0/1 is selected as one of the input clock sources. This must be connected to the ODIV2 output of the gtsouthrefclk0/1_in input buffer. The ODIV2 output must be configured to output a divided-by-1 clock.
gtnorthrefclk00_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTNORTHREFCLK0 is selected as one of the input clock sources and QPLL0 is active. You must instantiate input buffers at the system level. Connects to GTNORTHREFCLK00.
gtnorthrefclk01_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTNORTHREFCLK0 is selected as one of the input clock sources and QPLL1 is active. You must instantiate input buffers at the system level. Connects to GTNORTHREFCLK01.
gtnorthrefclk10_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTNORTHREFCLK1 is selected as one of the input clock sources and QPLL0 is active. You must instantiate input buffers at the system level. Connects to GTNORTHREFCLK10.
gtnorthrefclk11_in¹	I		. You must instantiate input buffers at the system level. Connects to GTNORTHREFCLK11.
gtsouthrefclk00_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTSOUTHREFCLK0 is selected as one of the input clock sources and QPLL0 is active. You must instantiate input buffers at the system level. Connects to GTSOUTHREFCLK00.
gtsouthrefclk01_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTSOUTHREFCLK0 is selected as one of the input clock sources and QPLL1 is active. You must instantiate input buffers at the system level. Connects to GTSOUTHREFCLK01.
gtsouthrefclk10_in¹	I		Available whenAvailable when Advanced Clock mode is enabled (DisplayPort) or when GTSOUTHREFCLK1 is selected as one of the input clock sources and QPLL0 is active. You must instantiate input buffers at the system level. Connects to GTSOUTHREFCLK10.
gtsouthrefclk11_in¹	I		Available when Advanced Clock mode is enabled (DisplayPort) or when GTSOUTHREFCLK1 is selected as one of the input clock sources and QPLL1 is active. You must instantiate input buffers at the system level. Connects to GTSOUTHREFCLK11.
gteastrefclk(0/1)_in (For HDMI and GTPE2 devices)	I		Available when GTEASTREFCLK0/1 is selected as one of the input clock sources. Connects to GTEASTREFCLK0/1 ports.
gtwestrefclk(0/1)_in (For HDMI and GTPE2 devices)	I		Available when GTWESTREFCLK0/1 is selected as one of the input clock sources. Connects to GTWESTREFCLK0/1 ports.
drpclk¹	I		Free running clock that is used to bring up the UltraScale device GT and to clock GT helper blocks.
vid_phy_tx_axi4s_aclk	I		Transmit AXI4-Stream Link Data interface clock
vid_phy_tx_axi4s_aresetn	I	TXUSRCLK2	Transmit AXI4-Stream Link Data interface reset. Unused port. It can be tied High or left unconnected.
vid_phy_rx_axi4s_aclk	I		Receive AXI4-Stream Link Data interface clock.
vid_phy_rx_axi4s_aresetn	I	RXUSRCLK2	Receive AXI4-Stream Link Data interface reset. Unused port. It can be tied High or left unconnected.
vid_phy_sb_aclk	I		Sideband interface clock. Connect to AXI4-Lite clock.
vid_phy_sb_aresetn	I	vid_phy_sb_aclk (AXI4-Lite)	Sideband interface reset. Unused port. It can be tied High, left unconnected or connected to the ARESETN port of the PROC_SYS_RESET IP under vid_phy_sb_aclk clock domain.
txoutclk	O		Buffered clock sent out for programmable logic. Available in HDMI when TX is enabled.
rxoutclk	O		Buffered clock sent out for programmable logic. Available in HDMI when RX is enabled.
vid_phy_axi4lite_aclk	I		AXI Bus clock.
vid_phy_axi4lite_aresetn	I	AXI4-Lite	AXI reset. active-Low. Must be connected to ARESETN that is synched to vid_phy_axi4lite_aclk port (that is, peripheral_aresetn port of Processor System Reset IP)
tx_refclk_rdy²	I	Async	Active-High (default): 1- Locked 0 - Unlocked TX reference clock ready or lock indicator. See the HDMI Reference Clock Requirements (link below) for details about the tx_refclk_rdy port implementation. Active level is controlled by Tx RefClk Rdy active AMD Vivado™ IDE parameter. If set to Low, 1 - Unlocked 0 - Locked
tx_tmds_clk²	O		TX TMDS clock.
tx_tmds_clk_p/n	O		Differential TX TMDS clock output. Note: These ports are disabled when Vivado IDE option "Use fourth GT Channel as TX TMDS Clock" is checked.
tx_video_clk²	O		TX video clock.
txrefclk_ceb²	O	AXI4-Lite	TX external reference clock IBUFDS CEB. Available when TX selects reference clock source from NORTH, SOUTH, EAST, or WEST. Example GTNORTHREFCLK_0/1.
rx_tmds_clk²	O		RX TMDS clock.
rx_tmds_clk_p/n²	O		Differential RX TMDS clock output.
rx_video_clk²	O		RX Video clock.
rxrefclk_ceb²	O	AXI4-Lite	RX external reference clock IBUFDS CEB. Available when RX selects reference clock source from NORTH, SOUTH, EAST, or WEST. Example GTNORTHREFCLK_0/1.
Used for UltraScale and UltraScale+ devices. Used for HDMI.

Clocking and Reset Interface Ports - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)