The GTX transceiver in 7 series FPGAs has two types of PLLs, the Quad PLL (QPLL) and the CPLL. The QPLL is shared by all four transceivers in the Quad. Each transceiver has its own CPLL. The Video PHY Controller IP allows you to choose whether the QPLL or the CPLL is used by the transmitter. The receiver should use the other PLL that is not used by TX.
The GTX transceivers can either use the QPLL or the Channel PLL (CPLL) as the clock source for the RX and the TX. The RX and the TX can use the same PLL or different PLLs. If the same PLL is used, for example, both use the CPLL, then they are "bonded" and must always run at exactly the same line rate. Take note that using bonded mode can only be done in the software by setting both TXSYSCLKSEL (and TXPLLCLKSEL) and RXSYSCLKSEL (and RXPLLCLKSEL) bits of RCS register to CPLL or QPLL. Setting the same PLL selection for TX and RX in the Video PHY Controller Vivado IDE causes a parameter validation error. While on bonded mode, note that the resolutions that require DRU cannot be transmitted by the Video PHY Controller core because the TX is being clocked by the DRU REFCLK (125 MHz). The TX REFCLK must run at its own clock, which is TX TMDS clock * Oversampling Factor to properly transmit lower resolutions.
The QPLL and the CPLL both have certain limitations. The QPLL has "holes" that are certain line rates that it cannot support due to the limited frequency range of its VCO. However, the QPLL can support lower TMDS clock frequencies than the CPLL
The CPLL voltage controlled oscillator (VCO) must run in the range of 1.6 GHz to 3.3 GHz. The VCO frequency is dependent upon the TMDS clock frequency. The CPLL can apply a limited set of multipliers to the TMDS clock frequency. The GT driver measures the TMDS clock frequency and attempts to find a valid multiplier that results in a VCO frequency that is within the allowed range.
Because the largest multiplier that can be applied by the CPLL is 20, the minimum TMDS clock frequency that the CPLL can support is 80 MHz. The CPLL does not support video formats that have a TMDS clock frequency of less than 80 MHz. When the GT driver detects that the TMDS clock frequency is less than 80 MHz, it enables the NI-DRU to receive these low bit rates that are less than 0.8 Gbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that the CPLL cannot support. For TMDS clock frequencies greater than 80 MHz, a multiplier of 10X or 20X is applied to keep the VCO frequency in the proper range as shown in the following table.
TMDS Clock Frequency (MHz) | CPLL Refclk Divider | CPLL Multiplier | VCO Frequency | Notes |
---|---|---|---|---|
<80 |
TX: Line Rate Dependent RX: 2 |
TX: Line Rate Dependent RX: 20 |
TX: Line Rate Dependent RX: 2.5 GHz |
TX: Oversampling RX: NI-DRU is used |
80 to 165 | 1 | 20 | 1.6 to 3.3 GHz | CDR is used |
165 to 330 | 1 | 10 | 1.65 to 3.3 GHz | CDR is used |
The CPLL can support all video formats. It has no "holes." However, the CPLL does require the use of the NI-DRU to cover any format that has a TMDS clock below 80 MHz. The following table shows the standard formats that are supported by the CPLL, indicating which requires the DRU.
The following table is for illustration only. For unlisted color formats, support might be possible if they are not restricted by the VCO frequency range.
Resolution (Hz) | Bits Per Pixel | |||
---|---|---|---|---|
24 | 30 | 36 | 48 | |
480i60 | DRU | DRU | DRU | DRU |
576i50 | DRU | DRU | DRU | DRU |
1080i50 | DRU | √ | √ | √ |
1080i60 | DRU | √ | √ | √ |
480p60 | DRU | DRU | DRU | DRU |
576p50 | DRU | DRU | DRU | DRU |
720p50 | DRU | √ | √ | √ |
720p60 | DRU | √ | √ | √ |
1080p24 | DRU | √ | √ | √ |
1080p25 | DRU | √ | √ | √ |
1080p30 | DRU | √ | √ | √ |
1080p50 | √ | √ | √ | √ |
1080p60 | √ | √ | √ | √ |
2160p24 | √ | √ | √ | √ |
2160p25 | √ | √ | √ | √ |
2160p30 | √ | √ | √ | √ |
2160p60 | √ | (1) | (1) | (1) |
vgap60 | DRU 3 | DRU | DRU | DRU 3 |
svgap60 | DRU | DRU | DRU | √ |
xgap60 | DRU | √ | √ | √ |
sxgap60 | √ | √ | √ | √ |
wxgap60 | DRU | √ | √ | √ |
wxga+p60 | √ | √ | √ | √ |
uxgap60 | √ | √ | √ | (2) |
wuxgap60 | √ | √ | √ | √ |
wsxga+p60 | √ | √ | √ | √ |
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When the QPLL is used as the clock source for either the RX or TX, there are combinations of resolutions, color depth, and color space that cannot be supported because the QPLL cannot generate the necessary clock frequencies to support those video formats. HDMI uses the lower band of QPLL. The VCO of the QPLL must run in the frequency range of 5.93 GHz to 8.0 GHz. The QPLL can apply multipliers of 20, 40, or 80 to the TMDS clock.
When the GT driver detects that the TMDS clock frequency is less than 74.125 MHz, it enables the NI-DRU to receive these lower bit rates that are less than 0.74125 Gbps. The NI-DRU runs at 2.0 Gbps, which enables it to recover line rates that the QPLL cannot support.
The following table shows how the TMDS clock frequency interacts with the QPLL and the frequency ranges that can be supported.
TMDS Clock Frequency (MHz) | QPLL Multiplier | Notes |
---|---|---|
This format is not supported because it exceeds the<74.125 |
TX: Line Rate Dependent RX: 40 |
TX: Oversampling 1 RX: NI-DRU is used |
74.125 to 100 | 80 | Supported |
100 to 148.25 | – | TMDS clock range cannot be supported |
148.25 to 200 | 40 | Supported |
200 to 296.5 | – | TMDS clock range cannot be supported |
296.5 to 400 | 20 | Supported |
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The following table shows which of the standard RGB and YCbCr 4:4:4 video formats are supported when using the QPLL. The QPLL supports formats shown with a check mark. Formats with the “–” are not supported because they fall into QPLL holes. Formats that require the DRU to receive them are noted in the table.
The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.
Resolution (Hz) | Bits Per Pixel | |||
---|---|---|---|---|
24 | 30 | 36 | 48 | |
480i60 | DRU | DRU | DRU | DRU |
576i50 | DRU | DRU | DRU | DRU |
1080i50 | √ | √ | – | √ |
1080i60 | √ | √ | – | √ |
480p60 | DRU | DRU | DRU | DRU |
576p50 | DRU | DRU | DRU | DRU |
720p50 | √ | √ | – | √ |
720p60 | √ | √ | – | √ |
1080p24 | √ | √ | – | √ |
1080p25 | √ | √ | – | √ |
1080p30 | √ | √ | – | √ |
1080p50 | √ | √ | – | √ |
1080p60 | √ | √ | – | √ |
2160p24 | √ | √ | – | √ |
2160p25 | √ | √ | – | √ |
2160p30 | √ | √ | – | √ |
2160p60 | √ | (1) | (1) | (1) |
vgap60 | DRU | DRU | DRU | DRU |
svgap60 | DRU | DRU | DRU | DRU |
xgap60 | DRU | √ | √ | – |
sxgap60 | – | – | √ | – |
wxgap60 | DRU | √ | – | – |
wxga+p60 | √ | – | – | √ |
uxgap60 | √ | – | – | (2) |
wuxgap60 | √ | – | – | √ |
wsxga+p60 | – | √ | – | – |
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