CPLL Use - 2.2 English

Because the largest multiplier that can be applied by the CPLL is 40, the minimum TMDS clock frequency that the CPLL can support is 50 MHz. Video formats that have a TMDS clock frequency of less than 50 MHz are not supported by the CPLL.

When the GT driver detects that the TMDS clock frequency is less than 50 MHz, it enables the NI-DRU to receive these low bit rates that are less than 500 Mbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that the CPLL cannot support.

For TMDS clock frequencies greater than 50 MHz, a multiplier of 10X, 20X, or 40X is applied to keep the VCO frequency in the proper range as shown in the following table.

The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.

When using the two Quad PLL (QPLL) types for the HDMI transmitter and receiver, line rate restrictions are introduced due to the VCO range and limited set of multipliers of the QPLL. The Video PHY Controller core driver dynamically switches between QPLL0 and QPLL1 to overcome these restrictions with QPLL0 having the priority if the TMDS clock frequency falls within the valid range of QPLL0 and QPLL1. For the transmitter, the Video PHY Controller core driver uses oversampling and the dynamic QPLL switching to work around the QPLL limitations.