The clock domain for the following table is the AXI4-Lite clock.
| Name | I/O | Description |
|---|---|---|
| vid_phy_axi4lite_awaddr[9:0] | I | Write address |
| vid_phy_axi4lite_awprot[2:0] | I | Protection type |
| vid_phy_axi4lite_awvalid | I | Write address valid |
| vid_phy_axi4lite_awready | O | Write address ready |
| vid_phy_axi4lite_awdata[31:0] | I | Write data bus |
| vid_phy_axi4lite_awstrb[3:0] | I | Write strobes |
| vid_phy_axi4lite_wvalid | I | Write valid |
| vid_phy_axi4lite_wready | O | Write ready |
| vid_phy_axi4lite_bresp[1:0] | O | Write response |
| vid_phy_axi4lite_bvalid | O | Write response valid |
| vid_phy_axi4lite_bready | I | Response ready |
| vid_phy_axi4lite_araddr[9:0] | I | Read address |
| vid_phy_axi4lite_arprot[2:0] | I | Protection type |
| vid_phy_axi4lite_arvalid | I | Read address valid |
| vid_phy_axi4lite_arready | O | Read address ready |
| vid_phy_axi4lite_rdata[31:0] | O | Read data |
| vid_phy_axi4lite_rresp[1:0] | O | Read response |
| vid_phy_axi4lite_rvalid[1:0] | O | Read valid |
| vid_phy_axi4lite_rready | I | Read ready |
| irq | O | Interrupt output |