GTXE2 - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Figure 1. GTXE2
Figure 2. Video PHY Controller GTXE2 GT Channel 4 as TX TMDS Clock Source

The following parameters affect the clocking of the GTXE2 device.

Adv_Clk_Mode
Configured through a check box in GUI.

This controls where the IBUFDS_GTE2 clock buffers of MGTREFCLK0 and MGTREFCLK1 are placed. When disabled, IBUFDS_GTE2 is placed within VPHY, but when enabled, IBUFDS_GTE2 should be manually instantiated at the system level. This is an ideal mode for applications requiring reference clock sharing across multiple VPHY instances.

C_Tx_Refclk_Fabric_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the TX REFCLK input clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Dru_Refclk_Fabric_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the DRU REFCLK input clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Rx_Tmds_Clk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the RX REFCLK input clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Tx_Tmds_Clk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the TX TMDS output clock

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Tx_Video_Clk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the TX Video output clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Tx_Outclk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the TX Link output clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Rx_Outclk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the RX Link output clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Rx_Video_Clk_Buffer
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls the type of buffer to be used for driving the fabric associated with the RX Video output clock.

Valid parameters: none, bufg, bufh, bufmr, and bufr.

C_Use_Oddr_for_Tmds_Clkout
Configured through a Tcl command or through the Block Properties Window in IP integrator. This controls whether an ODDR is inserted to drive the OBUFTDS for differential TX and RX TMDS output clocks.

Valid parameters: TRUE or FALSE.

C_Use_GT_CH4_HDMI
Configured through a check box in the Vivado IDE, through a Tcl command, or through the Block Properties Window in IP integrator. This controls whether a fourth GT channel is used in generating and transmitting the differential TX TMDS Clock (tx_tmds_clk_p/n).

Valid parameters: TRUE or FALSE.