Table 1. TX Initialization Register
Bit |
Default Value |
Access Type |
Description |
Channel 1 |
0 |
0 |
RW |
GTTXRESET |
1 |
0 |
RW |
TXPMARESET |
2 |
0 |
RW |
TXPCSRESET |
3 |
0 |
RW |
TXUSERRDY |
6:4 |
0 |
RW |
Reserved |
7 |
0 |
RW |
PLL_GT_RESET |
Channel 2 |
8 |
0 |
RW |
GTTXRESET |
9 |
0 |
RW |
TXPMARESET |
10 |
0 |
RW |
TXPCSRESET |
11 |
0 |
RW |
TXUSERRDY |
14:12 |
0 |
RW |
Reserved |
15 |
0 |
RW |
PLL_GT_RESET |
Channel 3 |
16 |
0 |
RW |
GTTXRESET |
17 |
0 |
RW |
TXPMARESET |
18 |
0 |
RW |
TXPCSRESET |
19 |
0 |
RW |
TXUSERRDY |
22:20 |
0 |
RW |
Reserved |
23 |
0 |
RW |
PLL_GT_RESET |
Channel 4 |
24 |
0 |
RW |
GTTXRESET |
25 |
0 |
RW |
TXPMARESET |
26 |
0 |
RW |
TXPCSRESET |
27 |
0 |
RW |
TXUSERRDY |
30:28 |
0 |
RW |
Reserved |
31 |
0 |
RW |
PLL_GT_RESET |