Known Issues - 2.2 English - PG230

Clock override critical warnings on TXOUTCLK or RXOUTCLK GT pins when compiling the DisplayPort and HDMI Video PHY Controller are known issues and can be ignored. This is necessary for constraining the GT pins per target maximum line rate. This is not normally a recommended flow but has been done for this specific case. The following is an example of the critical warning:

1. [Constraints 18-1056] Clock '<VPHY Path>/gtxe2_i/TXOUTCLK' completely overrides clock '<VPHY Path>/gtxe2_i/TXOUTCLK'.

   New: create_clock -period 3.704 [get_pins [list <VPHY Path>/gtxe2_i/TXOUTCLK <VPHY Path>/gtxe2_i/TXOUTCLK <VPHY Path>/gtxe2_i/TXOUTCLK <VPHY Path>/gtxe2_i/TXOUTCLK]], ["<Project Path>/project_1.srcs/sources_1/bd/design_1/ip/design_1_vid_phy_controller_0_0/vid_phy_controller_xdc.xdc": and 43]

   Previous: create_clock -period 24.692 [get_pins <VPHY Path>/gtxe2_i/TXOUTCLK], ["<Project Path>/project_1.srcs/sources_1/bd/design_1/ip/design_1_vid_phy_controller_0_0/ip_0/design_1_vid_phy_controller_0_0_gtwrapper.xdc": and 83]

2. Primary Clock declaration from the RX_CLKBUF_INST critical warnings on GTPE2 can be ignored. This is not normally a recommended flow but has been done for this specific case. Below is an example of the critical warning:

   A primary clock my_ip_dru_clk_b0gt0 is created on an inappropriate pin DUT/inst/RX_LCLK_BUF_INST/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)
   
   A primary clock my_ip_dru_clk_b0gt1 is created on an inappropriate pin DUT/inst/RX_LCLK_BUF_INST/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)
   
   A primary clock my_ip_dru_clk_b0gt2 is created on an inappropriate pin DUT/inst/RX_LCLK_BUF_INST/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)
   
   A primary clock my_ip_lclk_from_rxpll is created on an inappropriate pin DUT/inst/RX_LCLK_BUF_INST/O. It is recommended to create a primary clock only on a proper clock source (input port or primitive output pin with no timing arc)

   Note: TIMING-2 on GTP is by design. TIMING-17 is by design and can be ignored. The following is an example of a critical warning.

   TIMING-17#1 Critical Warning
   Non-clocked sequential cell 
   The clock pin DUT/inst/tx_tmdsclk_patgen_inst/txdata_counter_reg[0]/C is not reached by a timing clock