DisplayPort Clocking - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID

PG230

Release Date

2023-11-03

Version

2.2 English

The frequency details of the reference clock and the link clock are provided in the following table.

Table 1. Reference Clock and Link Clock Frequency Details of DisplayPort 1.2 TX
Family	Link Rate (Gbps)	TX Link Clock (MHz)		Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Family	Link Rate (Gbps)	GT Data Width = 2	GT Data Width = 4	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Kintex 7 GTX	1.62	81	40.5	On-board clock	135	CPLL
	2.7	135	67.5	On-board clock	135	CPLL
	5.4	270	135	On-board clock	135	CPLL
Virtex 7 GTH	1.62	81	40.5	On-board clock	135	CPLL
	2.7	135	67.5	On-board clock	135	CPLL
	5.4	270	135	On-board clock	135	CPLL
AMD UltraScale™ GTH3 AMD UltraScale+™ GTHE4	1.62	81	40.5	On-board clock	135	QPLL1
	2.7	135	67.5	On-board clock	135	QPLL1
	5.4	270	135	On-board clock	135	QPLL1

Table 2. Reference Clock and Link Clock Frequency Details of DisplayPort 1.2 RX
Family	Link Rate (Gbps)	RX Link Clock (MHz)		Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Family	Link Rate (Gbps)	GT Data Width = 2	GT Data Width = 4	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Kintex 7 GTX	1.62	81	40.5	DP159	81	CPLL
	2.7	135	67.5	DP159	135	CPLL
	5.4	270	135	DP159	270	CPLL
Virtex 7 GTH	1.62	81	40.5	DP159	81	CPLL
	2.7	135	67.5	DP159	135	CPLL
	5.4	270	135	DP159	270	CPLL
UltraScale GTH3 UltraScale+ GTHE4	1.62	81	40.5	DP159	81	CPLL
	2.7	135	67.5	DP159	135	CPLL
	5.4	270	135	DP159	270	CPLL

Table 3. Reference Clock and Link Clock Frequency Details of DisplayPort 1.4 TX
Family	Link Rate (Gbps)	TX Link Clock (MHz)	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Family	Link Rate (Gbps)	GT Data Width = 2	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
UltraScale GTH3 UltraScale+ GTHE4/GTYE4	1.62	81	On-board clock	270	QPLL1
	2.7	135	On-board clock	270	QPLL1
	5.4	270	On-board clock	270	QPLL1
	8.1	405	On-board clock	270	QPLL1

Table 4. Reference Clock and Link Clock Frequency Details of DisplayPort 1.4 RX
Family	Link Rate (Gbps)	RX Link Clock (MHz)	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
Family	Link Rate (Gbps)	GT Data Width = 2	Reference Clock Source	Reference Clock Frequency (MHz)	PLL Type
UltraScale GTH3 UltraScale+ GTHE4/GTYE4	1.62	81	On-board clock	270	CPLL
	2.7	135	On-board clock	270	CPLL
	5.4	270	On-board clock	270	CPLL
	8.1	405	On-board clock	270	CPLL

Important: Transmit Buffer Bypass must be enabled for the DisplayPort version 1.2 specification PHY compliance. This is required to pass the Inter-pair Skew Test in the DisplayPort 1.2 specification source device compliance tests. This test is only informative for the DisplayPort 1.4 specification-compliant source.

Important: Digital VCXO Replacement (PICXO) is not supported by the Video PHY Controller. For a field-customized Video PHY Controller that uses PICXO, the Transmit Buffer Bypass must be disabled, as it is a PICXO requirement. The Video PHY Controller is started up with Transmit Buffer Bypass enabled, and then switched to Transmit Buffer Bypass disabled during PICXO operation.