HDMI Clocking - 2.2 English

HDMI Clocking - 2.2 English - PG230

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID

PG230

Release Date

2023-11-03

Version

2.2 English

Important: The Transmit Buffer Bypass is always enabled for HDMI PHY compliance.

The HDMI core clocking diagrams per transceiver type are shown below. Follow the guidelines below when connecting the Video PHY Controller clock ports or refer to the HDMI example design.

Connect the external clock generator output clock to the TX reference clock input that was selected in the Video PHY Controller AMD Vivado™ IDE. The TX reference clock lock indicator should be connected to the tx_refclk_rdy port. See HDMI Reference Clock Requirements for its implementation.
Connect the RX TMDS clock from the external HDMI retimer component clock output to the corresponding RX reference clock input that was selected in the Video PHY Controller IDE.
If NI-DRU is enabled, connect the DRU reference clock to the DRU reference clock input that was selected in the Video PHY Controller IDE. See HDMI Reference Clock Requirement for the NI-DRU frequency requirements.
The txoutclk_out/rxoutclk_out signal is connected to the link_clk of the HDMI MAC controller.
The tx_video_clk/rx_video_clk signals are connected to the video_clk of HDMI MAC controller.
The tx_tmds_clk_p/n signal should be connected to the HDMI TX connector.
The tx_tmds_clk signal can be connected to any logic, for example, an audio generator module.
The rx_tmds_clk_p/n signal should be connected to the input of the external clock generator if the Video PHY Controller is used in pass through mode. This is to have a phase-aligned and jitter-attenuated reference clock for the HDMI TX Subsystem.
The rx_tmds_clk signal can be connected to any logic.
Tip: The tx_tmds_clk and rx_tmds_clk clock is the same as TMDS Clock in HDMI 2.0b Specification. For more information, see Section 6 in the HDMI 2.0b Specification.

Note: The HDMI RX and TX Subsystem clocks must be phase aligned in pass through mode to ensure seamless video streaming. Otherwise, the video output intermittently breaks due to mismatching clocks.

The following clocking diagrams show the default clock buffers used per device type. You can change these buffers as per your application's requirements using the user-configurable parameters. These parameters are in white dash-lined boxes with the prefix CONFIG.<user_param_name>.

Important: The Video PHY Controller has been tested using the default settings. You are expected to understand the proper clock buffer usage and design implications when changing the user parameters. See the 7 Series FPGAs Clocking Resources User Guide (UG472) and the UltraScale Architecture Clocking Resources User Guide (UG572).

The user parameters can be configured using Tcl commands or through the Block Properties window in IP integrator. For example:

set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>]
set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip name>]
set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>]

The HDMI clock structure is illustrated in the following figure and table.

Figure 1. HDMI Clocking Structure

Table 1. HDMI Clocking
Clock	Function	Freq/Rate	Example
TMDS	Source synchronous clock to HDMI interface (This is the actual clock on the HDMI cable).	= 1/10 data rate (for data rates < 3.4 Gbps) = 1/40 data rate (for data rates > 3.4 Gbps)	Data rate = 2.97 Gbps TMDS clock = 2.97/10 = 297 MHz Data rate = 5.94 Gbps TMDS clock = 5.94/40 = 148.5 MHz
Data	This is the actual data rate clock. This clock is not used in the system. It is only listed to illustrate the clock relations.	= TMDS clock (for data rates < 3.4 Gbps) = TMDS clock * 4 (for data rates > 3.4 Gbps)	Data rate = 2.97 Gbps Data clock = TMDS clock * 1 = 297 MHz Data rate = 5.94 Gbps Data clock = TMDS clock * 4 = 594 MHz TMDS clock = 148.5 MHz
Link	Clock used for data interface between the Video PHY layer module and subsystem	For dual pixel video: Clock=data clock/2 For quad pixel video: clock=data clock/4	TMDS clock = 297 MHz Data clock = 297 MHz Link clock = 297 MHz/2=148.5 MHz for dual pixel wide interface Link clock = 297 MHz/4 = 74.25 MHz for quad pixel wide interface Data clock = 594 MHz Link clock = 594 MHz/2=297 MHz for dual pixel wide interface Link clock = 594 MHz/4=148.5 MHz for quad pixel wide interface
Pixel	This is the internal pixel clock. This clock is not used in the system. It is only listed to illustrate the clock relations.	For 8 bpc pixel clock = data clock For 10 bpc pixel clock = data clock/1.25 For 12 bpc pixel clock = data clock/1.5 For 16 bpc pixel clock = data clock/2	Data clock = 297 MHz For 8 bpc pixel clock = 297 MHz For 10 bpc pixel clock = 297/1.25 = 237.6 MHz For 12 bpc pixel clock = 297/1.5 = 198 MHz For 16 bpc pixel clock = 297/1.5 = 148.5 MHz
Video	Clock used for video interface	For dual pixel video clock = pixel clock/2 For quad pixel video clock = pixel clock/4	297 MHz/2 = 148.5 MHz for dual pixel wide interface 297 MHz/4 = 74.25 MHz for quad pixel wide interface

For example, 1080p60, 12 BPC, and 2 PPC are used to show how all the clocks are derived.

Table 2. Example Settings
Video Resolution	Horizontal Total	Horizontal Active	Vertical Total	Vertical Active	Frame Rate (Hz)
1080p60	2200	1920	1125	1080	60

For example, 8kp30, 8 BPC, 4 PPC are used to show how all the clocks are derived.

The pixel clock represents the total number of pixels that need to be sent every second.

Pixel clock = Htotal × Vtotal × Frame Rate =2200 x 1125 x 60 =148,500,000 = 148.5 MHz
Video clock = (Pixel clock)/PPC=148.5/2=74.25 MHz
Data clock = Pixel clock × BPC/8=148.5× 12/8=222.75 MHz
Link clock = (Data clock)/PPC=222.75/2=111.375 MHz

Using the associative property in this example,

Data clock = 222.75 MHz < 340 MHz

then

TMDS clock = Data clock = 222.75 MHz

Note: : For resolutions less than the supported rate, TX uses oversampling and RX uses NI-DRU logic.