The following control is transferred from the Link Layer. The control bits are driven using the AXI4-Lite clock.
| Bit Position | Status Details |
|---|---|
| 0 |
Training Iteration GT Reset. Pulse generated for every access of the DPCD TRAINING_LANE0_SET register which can be used to reset the GT to eliminate buffer errors and bad CDR locks. |
| 1 |
Start of TP1 Reset. Pulse generated whenever TP1 pattern starts. This can be used to reset the GT for a clean start of training sequence. |