DisplayPort Receive - Control Path - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

The following control is transferred from the Link Layer. The control bits are driven using the AXI4-Lite clock.

Table 1. DisplayPort Receive Control Sideband Definition
Bit Position Status Details

Training Iteration GT Reset.

Pulse generated for every access of the DPCD TRAINING_LANE0_SET register which can be used to reset the GT to eliminate buffer errors and bad CDR locks.


Start of TP1 Reset.

Pulse generated whenever TP1 pattern starts. This can be used to reset the GT for a clean start of training sequence.