Core Overview - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

The Video PHY Controller core is a feature-rich soft IP core that incorporates all the necessary logic to properly interface with media access control (MAC) layers and perform physical-side interface (PHY) functionality. AMD IP cores have been successfully tested on hardware and verified. For additional details on the interoperability results, contact your local AMD sales representative.

The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP is not intended to be used as a standalone IP and must be used with AMD Video MACs, such as the HDMI™ 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems . The core enables simpler connectivity between MAC layers for TX and RX paths. However, it is still important to understand the behavior, use, and limitations of the transceivers. For more information, see UltraScale Architecture GTH Transceivers User Guide (UG576) and UltraScale Architecture GTY Transceivers User Guide (UG578).

The following figure shows the standard OSI Model and mapping it with video IP solutions.

Figure 1. OSI Mapping of Video Systems

In accordance with the OSI model, the major PHY component for video IP cores is SerDes. Standardizing the SerDes delivery model provides benefits and flexibility for a video MAC layer at the system level.

The following figure shows the boundary between these MAC and PHY layers and the key highlights are:
  • AXI4-Lite interface to provide software access.
  • AXI4-Stream-based GT channel interface for easier connectivity between different video link layers. (GT is also referred to as a serial transceiver.)
Figure 2. Video IP Layer