The Video PHY Controller is designed to
operate in coordination with the performance characteristics of the transceiver primitives
it instantiates:
- For the DisplayPort 1.2 protocol, a 2-byte and 4-byte internal datapath are configured.
- For the DisplayPort 1.4 protocol, only a 2-byte internal datapath is supported.
The following documents provide information about DC and AC switching characteristics. The frequency ranges specified by these documents must be adhered to for proper transceiver and core operation:
- Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
- Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
- Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
- Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
- Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893)
- Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892)
- Zynq 7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100) Data Sheet: DC and AC Switching Characteristics (DS191)
- Kintex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182)
- Virtex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183)
- Artix 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181)
- Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)