TX Status (TXS) Register (0x0078) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. TX Status (TXS) Register
Bit Default Value Access Type Description
Channel 1
0 0 RW TXPHALIGNDONE
1 0 RW TXPHINITDONE 1
2 0 RW TXDLYRESETDONE 1
4:3 0 RW TXBUFSTATUS[1:0]
5 0 RW TXBUFFBYPASS_ERROR (UltraScale and UltraScale+ devices)
7:6 0 RW Reserved
Channel 2
8 0 RW TXPHALIGNDONE
9 0 RW TXPHINITDONE 1
10 0 RW TXDLYRESETDONE 1
12:11 0 RW TXBUFSTATUS[1:0]
13 0 RW TXBUFFBYPASS_ERROR (UltraScale and UltraScale+ devices)
15:14 0 RW Reserved
Channel 3
16 0 RW TXPHALIGNDONE
17 0 RW TXPHINITDONE 1
18 0 RW TXDLYRESETDONE 1
20:19 0 RW TXBUFSTATUS[1:0]
21 0 RW TXBUFFBYPASS_ERROR (UltraScale and UltraScale+ devices)
23:22 0 RW Reserved
Channel 4
24 0 RW TXPHALIGNDONE
25 0 RW TXPHINITDONE 1
26 0 RW TXDLYRESETDONE 1
28:27 0 RW TXBUFSTATUS[1:0]
29 0 RW TXBUFFBYPASS_ERROR (UltraScale and UltraScale+ devices)
31:30 0 RW Reserved
  1. For the DisplayPort protocol, this register field is unused.