PLL Reset Register (PR) (0x0014) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Note:

This is applicable only to the DisplayPort. It is not used in HDMI.

Table 1. PLL Reset Register
Bit Default Value Access Type Description
0 0 RW CPLLRESET
1 0 RW QPLL0RESET
2 0 RW QPLL1RESET – For UltraScale and UltraScale+ devices