HDMI Receive - Status Path - HDMI Receive - Status Path - 2.2 English - PG230

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

The following status is transferred to the Link layer. The status bits are driven using the AXI4-Lite clock.

Table 1. HDMI Receive Status Sideband Definition
Bit Position Status Details
0 RX Link Ready. This signal is asserted to indicate that the GT RX initialization is completed (rxresetdone).
1 RX Video Ready. This signal is asserted to indicate that the video clock from the RX MMCM/PLL block is stable.
[7:2] Reserved.