The following status is transferred to the Link layer. The status bits are driven using the AXI4-Lite clock.
| Bit Position | Status Details |
|---|---|
| 0 | Bank 0, GT Channel 0, TX Reset Done |
| 1 | Based on TXSYSCLKSEL[0], CPLL Channel 0/QPLL Lock is transferred |
| 2 | Bank 1, GT Channel 1, TX Reset Done |
| 3 | Based on TXSYSCLKSEL[0], CPLL Channel 1/QPLL Lock is transferred |
| 4 | Bank 0, GT Channel 2, TX Reset Done |
| 5 | Based on TXSYSCLKSEL[2], CPLL Channel 2/QPLL Lock is transferred |
| 6 | Bank 0, GT Channel 3, TX Reset Done |
| 7 | Based on TXSYSCLKSEL[3], CPLL Channel 3/QPLL Lock is transferred |