RX Equalization and CDR Register (0x0108) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. RX Equalization and CDR Register
Bit Default Value Access Type Description
Channel 1
0 0 RW RXLPMEN
1 0 RW RXCDRHOLD 1
2 0 RW RXOSOVRDEN 1
3 0 RW RXLPMLFKLOVRDEN 1
4 0 RW RXLPMHFOVRDEN 1
5:7 0 RW Reserved
Channel 2
8 0 RW RXLPMEN
9 0 RW RXCDRHOLD 1
10 0 RW RXOSOVRDEN 1
11 0 RW RXLPMLFKLOVRDEN 1
12 0 RW RXLPMHFOVRDEN 1
15:13 0 RW Reserved
Channel 3
16 0 RW RXLPMEN
17 0 RW RXCDRHOLD 1
18 0 RW RXOSOVRDEN 1
19 0 RW RXLPMLFKLOVRDEN 1
20 0 RW RXLPMHFOVRDEN 1
23:21 0 RW Reserved
Channel 4
24 0 RW RXLPMEN
25 0 RW RXCDRHOLD 1
26 0 RW RXOSOVRDEN 1
27 0 RW RXLPMLFKLOVRDEN 1
28 0 RW RXLPMHFOVRDEN 1
31:29 0 RW Reserved
  1. For the DisplayPort protocol, this register field is unused.