High-Speed I/O - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

The three differential pairs of TX and RX high-speed lanes are implemented as GT TX and RX channels, respectively. Therefore, I/O standard constraints are not required. Board design and connectivity should follow HDMI standard recommendations.

For 7 series devices, actual pin assignments are required. Use the following constraints:

Sample Pin Assignments:

set_property PACKAGE_PIN E4 [get_ports {HDMI_RX_DAT_P_IN[0]}]
set_property PACKAGE_PIN D6 [get_ports {HDMI_RX_DAT_P_IN[1]}]
set_property PACKAGE_PIN B6 [get_ports {HDMI_RX_DAT_P_IN[2]}]

For UltraScale and UltraScale+ devices, actual pin assignments are absorbed by the GT Wizard instance in the Video PHY Controller. Therefore, pin assignment constraints are not required.