TMDS Clock - 2.2 English

The TX TMDS clock output is implemented as LVDS (LVDS25) I/O standard when the C_Use_GT_CH4_HDMI user parameters are set to false.

The RX TMDS and NI_DRU clock inputs are implemented as a GT reference clock input. Therefore, I/O standard constraints are not required.

For Kintex 7 and Artix 7 devices, use the following constraints:

IO Standard:

TX TMDS: set_property IOSTANDARD LVDS_25 [get_ports HDMI_TX_CLK_P_OUT]
RX TMDS & NI-DRU: N/A

Sample Pin Assignments:

TX TMDS: set_property PACKAGE_PIN C19 [get_ports HDMI_TX_CLK_P_OUT]
RX TMDS: set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN]
NI-DRU: set_property PACKAGE_PIN G8 [get_ports DRU_CLK_IN_clk_p]

For Virtex 7, UltraScale, and UltraScale+ devices, use the following constraints:

I/O Standard:

TX TMDS: set_property IOSTANDARD LVDS [get_ports HDMI_TX_CLK_P_OUT]
RX TMDS & NI-DRU: N/A

Sample Pin Assignments:

TX TMDS: set_property PACKAGE_PIN H21 [get_ports HDMI_TX_CLK_P_OUT]
RX TMDS: set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN]
NI-DRU: set_property PACKAGE_PIN G8 [get_ports DRU_CLK_IN_clk_p]

Board design and connectivity should follow the HDMI standard recommendations with proper level shifting or TMDS driver use.