User Parameters - 2.2 English

User Parameters - 2.2 English - PG230

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID

PG230

Release Date

2023-11-03

Version

2.2 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Vivado IDE Parameter/Value	User Parameter/Value	Default Value	Register Encoding
TX/RX Protocol Selection	C_Tx/Rx_Protocol	DP
DP
HDMI
None
TX/RX Max GT Line Rate	Tx/Rx_Max_GT_Line_Rate	8.1 for DP 1.4 for UltraScale and UltraScale+ devices 5.4 Gbps for DP 1.2 5.94 for HDMI
TX/RX Clock Primitive	C_Tx/Rx_Clk_Primitive	MMCM
TX/RX Channels	C_Tx/Rx_No_Of_Channels	4 for DP 3 for HDMI
Tx PLL Type¹	C_TX_PLL_SELECTION	3 for transceiver GTPE2 and GTXE2 2 for DP under transceiver GTHE3, GTHE4, and GTYE4 6 for HDMI under transceiver GTHE3, GTHE4, and GTYE4	TX/RXSYSCLKSEL TX/RXPLLCLKSEL
CPLL: 0			00
QPLL0: 1			TX/RXSYSCLKSEL: 10 TX/RXPLLCLKSEL: 11
QPLL1: 2			TX/RXSYSCLKSEL: 11 TX/RXPLLCLKSEL: 10
QPLL: 3			11
PLL0: 4			00
PLL1: 5			11
QPLL0/1: 6			Follow QPLL0 or QPLL1 encoding
Rx PLL Type¹	C_RX_PLL_SELECTION	0	Similar to TX PLL Type
Tx Ref Clock Selection¹	C_TX_REFCLK_SEL	1
GTREFCLK0: 0 GTREFCLK1: 1 GTNORTHREFCLK0: 2 GTNORTHREFCLK1: 3 GTSOUTHREFCLK0: 4 GTSOUTHREFCLK1: 5 GTEASTREFCLK0: 6 GTEASTREFCLK1: 7 GTWESTREFCLK0: 8 GTWESTREFCLK1: 9			001 010 011 100 101 110 011 100 101 110
Rx Ref Clock Selection¹	C_RX_REFCLK_SEL	0	Similar to Tx Ref Clock Selection
Tx Buffer Bypass	Tx_Buffer_Bypass	TRUE for HDMI false for DisplayPort
TX REFCLK Ready Active	C_Txrefclk_Rdy_Invert	false
Use 4th GT Channel as TX TMDS Clock	C_USE_GT_CH4_HDMI	High
NI-DRU	C_NIDRU	TRUE
NI-DRU Ref Clock Selection	C_NIDRU_REFCLK_SEL	0	Similar to Tx Ref Clock Selection
Advanced Clock Mode	Adv_Clk_Mode	false
Number of pixels per clock Value Selection 1 2 4	C_INPUT_PIXELS_PER_CLOCK	4
DRP Clock Frequency (MHz)	DRPCLK_FREQ	40 for DP 100 for HDMI
Transceiver Width Value Selection 2 4	Transceiver_Width	2
GT: Starting channel Location	CHANNEL_SITE	the lowest number from available X<num>Y<num> in GT
Use ODDR/ODDRE1 for TX and RX differential TMDS clock out	C_Use_Oddr_for_Tmds_Clkout³	TRUE
TX TMDS Clock output buffer 7 series: none, bufg, bufh, bufmr, bufr UltraScale/UltraScale+: none, bufg⁴	C_Tx_Tmds_Clk_Buffer³	none – for 7 series bufg – for UltraScale/UltraScale+
TX Video Clock output buffer 7 series: none, bufg, bufh, bufmr, bufr UltraScale/UltraScale+: none, bufg⁴	C_Tx_Video_Clk_Buffer³	bufg
RX TMDS Clock output buffer 7 series: none, bufg, bufh, bufmr, bufr UltraScale/UltraScale+: none, bufg⁴	C_Rx_Tmds_Clk_Buffer³	bufg
RX Video Clock output buffer 7 series: none, bufg, bufh, bufmr, bufr UltraScale/UltraScale+: none, bufg⁴	C_Rx_Video_Clk_Buffer³	bufg
TX Link Clock output buffer (7 series only) none, bufg, bufh, bufmr, bufr⁴	C_Tx_Outclk_Buffer³	bufg
TX REFCLK input buffer to fabric (7 series only) none, bufg, bufh, bufmr, bufr⁴	C_Tx_Refclk_Fabric_Buffer³	bufg
RX Link Clock output buffer (7 series only) none, bufg, bufh, bufmr, bufr⁴	C_Rx_Outclk_Buffer³	bufg
DRU REFCLK input buffer to fabric (7-series only) none, bufg, bufh, bufmr, bufr⁴	C_Dru_Refclk_Fabric_Buffer³	none
TX Phase Interpolator port enable (UltraScale and UltraScale+ only)	C_TXPI_Port_EN¹	none
The Vivado IDE Parameter/Values are only used for the Video PHY Controller IP configuration in the Vivado IDE and are not the actual register encoding used to configure the Reference Clock Selection Register at offset 0x0010. The Video PHY Controller driver converts these parameters to the corresponding register encoding in the Register Encoding column. The Vivado IDE Parameter/Values are only used for the Video PHY Controller IP configuration in Vivado environment and are not the actual register encoding used to configure the PLL REFCLKSEL bits (11:0) of the Reference Clock Selection Register at offset 0x0010. The Video PHY Controller driver converts these parameters to the corresponding register encoding in the Register Encoding column. The user parameter applies to HDMI only and can be configured through Tcl command or through the Block Properties Window in IP integrator. Example: `set_property -dict [list CONFIG.C_Tx_Outclk_Buffer {none}] [get_ips <ip name>] set_property -dict [list CONFIG.C_Rx_Video_Clk_Buffer {bufg}] [get_ips <ip name>] set_property -dict [list CONFIG.C_Use_Oddr_for_Tmds_Clkout {false}] [get_ips <ip name>] set_property -dict [list CONFIG.C_TXPI_Port_EN {true}] [get_ips <ip name>]` See Clocking.