HDMI Program and Interrupt Flow - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

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2.2 English

The Video PHY Controller core driver manages the dynamic reconfiguration of the multi-gigabit transceiver and digital clock manager modules to allow seamless transmission and reception of HDMI video to and from the FPGA physical interface.

The main program flow is shown in the following sections. At execution, the software application initializes the Video PHY Controller IP and registers the callback functions in the provided hooks. After the initialization, all API calls are interrupt triggered starting from either TX or RX reference clock change.

Note: The Video PHY Controller driver does not carry the video format, resolution, or color space information. The HDMI TX and RX MAC handle such information. See the HDMI 1.4/2.0 Transmitter Subsystem Product Guide (PG235) and HDMI 1.4/2.0 Receiver Subsystem Product Guide (PG236) for more information.