QPLL0 and QPLL1 Use - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

When using the two Quad PLL (QPLL) types for the HDMI transmitter and receiver, line rate restrictions are introduced due to the VCO range and limited set of multipliers of the QPLL. The Video PHY Controller core driver dynamically switches between QPLL0 and QPLL1 to overcome these restrictions with QPLL0 having the priority if the TMDS clock frequency falls within the valid range of QPLL0 and QPLL1. For the transmitter, the Video PHY Controller core driver uses oversampling and the dynamic QPLL switching to work around the QPLL limitations.

If the GT driver detects that the TMDS clock frequency is less than 61.25 MHz, it enables the NI-DRU to receive these lower bit rates that are less than 0.6125 Gbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that cannot be supported by the QPLL0. The Video PHY Controller does not use QPLL1 in NI-DRU mode.

The VCO of the QPLL0 must run in the frequency range of 9.8 GHz to 16.375 GHz. The QPLL0 can apply multipliers of 20, 40, 80, or 160 to the TMDS clock.

Important: The limited VCO range and the available multipliers of the QPLL0 cause gaps in the range of line rates that can be supported for the HDMI.

The following table shows how the TMDS clock frequency interacts with the QPLL0 and the frequency ranges that can be supported.

Table 1. UltraScale GTH QPLL0 Use
TMDS Clock Frequency (MHz) QPLL0 Multiplier Notes
<61.25

TX: Line Rate Dependent

RX: 64

TX: Oversampling

RX: NI-DRU is used

61.25 to 102.34375 160 Supported
102.34375 to 122.5 TMDS clock range cannot be supported
122.5 to 204.6875 80 Supported
204.6875 to 245 TMDS clock range cannot be supported
245 to 409.375 40 Supported
409.375 to 490 TMDS clock range cannot be supported

If the QPLL0 is used as the clock source, video formats with a TMDS clock of 102.34375 MHz to 122.5 MHz, 204.6875 MHz to 245 MHz, and frequencies higher than 409.375 MHz cannot be supported because a multiplier cannot be used to meet the valid VCO range.

The VCO of the QPLL1 must run in the frequency range of 8.0 GHz to 13.0 GHz. The QPLL1 can apply multipliers of 20, 40, 80, or 160 to the TMDS clock.

Important: The limited VCO range and the available multipliers of the QPLL1 cause gaps in the range of line rates that can be supported for HDMI.

The following table shows how the TMDS clock frequency interacts with the QPLL1 and the frequency ranges that can be supported.

If the QPLL1 is used as the clock source, video formats with a TMDS clock of 81.25 MHz to 100 MHz, 162.5 MHz to 200 MHz, and 325 MHz to 400 MHz cannot be received because a multiplier cannot be used to meet the valid VCO range.

Table 2. UltraScale GTH QPLL1 Use
TMDS Clock Frequency (MHz) QPLL1 Multiplier Notes
<50.0 N/A

TX: Oversampling

RX: NI-DRU is used

50.0 to 81.25 160 Supported
81.25 to 100 TMDS clock range cannot be supported
100 to 162.5 80 Supported
162.5 to 200 TMDS clock range cannot be supported
200 to 325 40 Supported
325 to 400 TMDS clock range cannot be supported
400 to 650 20 Supported

The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.

Table 3. QPLL Support of RGB and YCbCr 4:4:4 Video Formats
Resolution (Hz) Bits Per Pixel
24 30 36 48
480i60 DRU DRU DRU DRU
576i50 DRU
1080i50
1080i60
480p60 DRU DRU DRU DRU
576p50 DRU DRU DRU DRU
720p50
720p60
1080p24
1080p25
1080p30
1080p50
1080p60
2160p24
2160p25
2160p30
2160p60 (1) (1) (1)
VGA 60 DRU DRU DRU
SVGA 60 DRU DRU
XGA 60
SXGA 60
WXGA 60
WXGA + 60
UXGA 60
WUXGA 60
WSXGA 60
  1. This format is not supported in TMDS mode because it exceeds the maximum line rate of HDMI 2.0.
  2. This format is supported for transmit, but is not currently supported by the receiver.