7 Series GTPE2 HDMI Implementation - 2.2 English

The GTP transceiver in 7 series FPGAs has two types of PLLs, the PLL0 and PLL1 of similar characteristics. All four transceivers in the Quad share both PLL types. There is no dedicated PLL for each transceiver channel for GTPE2. The Video PHY IP enables you to choose whether the PLL0 or the PLL1 is used by the transmitter. The receiver should use the other PLL that TX does not use.

The PLL0/1 voltage controlled oscillator (VCO) must run in the range of 1.6 GHz to 3.3 GHz. The VCO frequency is dependent upon the TMDS clock frequency. The PLL0/1 can apply a limited set of multipliers to the TMDS clock frequency. The GT driver measures the TMDS clock frequency and attempts to find a valid multiplier that results in a VCO frequency that is within the allowed range.

Because the largest multiplier that the PLL0/1 applies is 20, the minimum TMDS clock frequency that the PLL0/1 can support is 80 MHz. Video formats that have a TMDS clock frequency of less than 80 MHz are not supported by the PLL0/1. When the GT driver detects that the TMDS clock frequency is less than 80 MHz, it enables the NI-DRU to receive these low bit rates that are less than 0.8 Gbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that the PLL0/1 cannot support. For TMDS clock frequencies greater than 80 MHz, a multiplier of 10X or 20X is applied to keep the VCO frequency in the proper range as shown in the following table.

The PLL0/1 can support all video formats. It has no "holes." However, the PLL0/1 does require the use of the NI-DRU to cover any format that has a TMDS clock below 80 MHz. The following table shows the standard formats that the PLL0/1 supports, indicating which requires the DRU.

The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.