RX Initialization (RXI) Register (0x0024) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. RX Initialization (RXI) Register
Bit Default Value Access Type Description
Channel 1
0 0 RW GTRXRESET
1 0 RW RXPMARESET
2 0 RW RXDFELPMRESET 1
3 0 RW RESERVED 2
4 0 RW RXPCSRESET 2
5 0 RW RXBUFRESET
6 0 RW RXUSERRDY 3
7 0 RW PLL_GT_RESET
Channel 2
8 0 RW GTRXRESET
9 0 RW RXPMARESET
10 0 RW RXDFELPMRESET 1
11 0 RW RESERVED 2
12 0 RW RXPCSRESET 2
13 0 RW RXBUFRESET
14 0 RW RXUSERRDY 3
15 0 RW PLL_GT_RESET
Channel 3
16 0 RW GTRXRESET
17 0 RW RXPMARESET
18 0 RW RXDFELPMRESET 1
19 0 RW RESERVED 2
20 0 RW RXPCSRESET 2
21 0 RW RXBUFRESET
22 0 RW RXUSERRDY 3
23 0 RW PLL_GT_RESET
Channel 4
24 0 RW GTRXRESET
25 0 RW RXPMARESET
26 0 RW RXDFELPMRESET 1
27 0 RW RESERVED 2
28 0 RW RXPCSRESET 2
29 0 RW RXBUFRESET
30 0 RW RXUSERRDY 3
31 0 RW PLL_GT_RESET
  1. For the DisplayPort protocol, RXDFELPMRESET is an unused field.
  2. For the DisplayPort protocol, this register field is unused for UltraScale and UltraScale+ devices.
  3. For the DisplayPort protocol, this register field is unused for UltraScale and UltraScale+ devices. The internal GT UltraScale wizard FSM handles this field.