DRP CONTROL MMCM TXUSRCLK Register (0x0124) - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English
Table 1. DRP CONTROL MMCM TXUSRCLK Register
Bit Default Value Access Type Description
11:0 0 RW DRPADDR[8:0]
12 0 RW DRPEN
13 0 RW DRPWE
14 0 RW DRP Reset (For UltraScale and UltraScale+ devices) 1
15 0 RW Reserved
31:16 0 RW DRPDI [15:0]
  1. For the DisplayPort protocol, this register field is unused.