Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal® ACAP design process Design Hubs and the Design Flow Assistant materials can be found on the Xilinx.com website. This document covers the following design processes:
- System and Solution Planning
- Identifying the components, performance, I/O, and data transfer requirements at a system level. Includes application mapping for the solution to PS, PL, and AI Engine. Topics in this document that apply to this design process include:
- Embedded Software Development
-
Creating the software platform from the hardware
platform and developing the application code using
the embedded CPU. Also covers XRT and Graph
APIs. Topics in this document that
apply to this design process include:
- QDMA Subsystem Register Space
- AXI Bridge Subsystem Register Space
- XDMA Subsystem Register Space
- Host Software Development
-
Developing the application code, accelerator
development, including library, XRT, and Graph API
use. Topics in this document that
apply to this design process include:
- QDMA Subsystem Register Space
- AXI Bridge Subsystem Register Space
- XDMA Subsystem Register Space
- Hardware, IP, and Platform Development
-
Creating the PL IP blocks for the hardware
platform, creating PL kernels, functional
simulation, and evaluating the
Vivado®
timing,
resource use, and power closure. Also involves
developing the hardware platform for system
integration. Topics in this document
that apply to this design process include:
- QDMA Subsystem Customizing and Generating the Subsystem
- AXI Bridge Subsystem Customizing and Generating the Subsystem
- XDMA Subsystem Customizing and Generating the Subsystem