AXI Memory Mapped Writeback Status Structure for H2C and C2H

AXI Memory Mapped Writeback Status Structure for H2C and C2H - 1.0 English

Versal ACAP DMA and Bridge Subsystem for PCI Express Product Guide (PG344)

Document ID

PG344

Release Date

2022-05-20

Version

1.0 English

The MM writeback status register is located after the last entry of the (H2C or C2H) descriptor.

Table 1. AXI Memory Mapped Writeback Status Structure for H2C and C2H
Bit	Bit Width	Field Name	Description
[63:48]	16	reserved	Reserved
[47:32]	16	pidx	Producer Index at time of writeback
[31:16]	16	cidx	Consumer Index
[15:2]	14	reserved	Reserved
[1:0]	2	err	Error bit 1: Descriptor fetch error bit 0: DMA error