| Bit Index | Default | Access Type | Description |
|---|---|---|---|
| 23:19 | 5’h0 | RW |
im_desc_error[4:0] Set to 1 to interrupt when corresponding status register read_error bit is logged. |
| 18:14 | 5’h0 | RW |
im_write_error[4:0] set to 1 to interrupt when corresponding status register write_error bit is logged. |
| 13:9 | 5’h0 | RW |
im_read_error[4:0] set to 1 to interrupt when corresponding status register read_error bit is logged. |
| 8:7 | Reserved | ||
| 6 | 1’b0 | RW |
im_idle_stopped Set to 1 to interrupt when the status register idle_stopped bit is logged. |
| 5 | 1’b0 | RW |
im_invalid_length Set to 1 to interrupt when status register invalid_length bit is logged. |
| 4 | 1’b0 | RW |
im_magic_stopped set to 1 to interrupt when status register magic_stopped bit is logged. |
| 3 | 1’b0 | RW |
im_align_mismatch set to 1 to interrupt when status register align_mismatch bit is logged. |
| 2 | 1’b0 | RW |
im_descriptor_completd set to 1 to interrupt when status register descriptor_completed bit is logged. |
| 1 | 1’b0 | RW |
im_descriptor_stopped set to 1 to interrupt when status register descriptor_stopped bit is logged. |